Various thin film layers for semiconductor devices may be deposited by chemical vapor deposition (CVD) and/or plasma-enhanced chemical vapor deposition (PECVD) processes. Some deposition processes generate small gas phase particles during process, which may decorate a deposition surface, potentially contaminating the device. Such particles may cling to the device, potentially blocking subsequent etch and/or deposition events, which may ultimately lead to device failure. Further, particles may be knocked off the device downstream, potentially contaminating other process tools.
Some approaches to addressing gas-phase particle generation may attempt to suppress particle generation by diluting reaction conditions. However, such approaches may diminish film deposition rates, requiring the installation and maintenance of additional process tools to support a production line. Further, films produced by such approaches may have physical or electrical characteristics that provide inadequate device performance. Further still, such approaches may not address particles formed in various exhaust hardware for the process tool, which may back-stream and contaminate the device. These particles may be delivered to the substrate surface during deposition. Once coated by additional film material, the small size of the particles may be magnified, causing ripples and distortions at the film surface. These ripples may make it difficult to pattern the resulting films.
Patterning problems may also be caused by rough films. Some traditional atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD) and plasma-enhanced chemical vapor deposition (PECVD) processes for depositing film layers may produce unacceptably rough films, cause unacceptable interfacial mixing between film layers, and may have interfacial defects caused by vacuum breaks between successively deposited film layers. The resulting rough film interfaces and interfacial defects may be magnified by subsequently deposited layers as the film stack is built, so that the top surface of the film stack may be unacceptably rough for downstream patterning processes. Further, interfacial defects within the film stack may lead to structural and/or electrical defects in the resulting integrated device.